International SoC Design Conference : October 15-16 : KoreaIn this paper, we develop a heterogeneous architecture for the reconfigurable functional unit of an extensible processor. To verify the efficiency of our architecture, we applied it to 8 applications of Mibench. The new architecture improves execution time of custom instructions by 20% to 30% on average while supporting more custom instructions. The area and the total wire length are reduced by 15% and 20% respectively. In addition, depending on the custom instructions being run on the unit, average dynamic power consumption is reduced by 9% making this unit more suitable for embedded applications
This paper describes an approach for adaptive dynamic instruction set extension, tuning processors t...
The relentless push in technology scaling driven by Moore's Law has witnessed fantastic gains in the...
Abstract This paper describes an approach for adaptive dynamic instruction set extension, tuning pro...
15th Annual IFIP International Conference on Very Large Scale Integration : VLSI-SoC 2007 : October ...
ABSTRACT- In this paper, we develop a heterogeneous architecture for the reconfigurable functional u...
This paper presents a reconfigurable functional unit (RFU) for an adaptive dynamic extensible proces...
A traditional extensible processor with customized circuits achieves high performance at the cost of...
In this research we investigate an approach for adaptive dynamic instruction set extension, tuning p...
To improve the performance of embedded processors, an effective technique is collapsing critical com...
To improve the performance of embedded processors, an effective technique is collapsing critical com...
Extracting appropriate custom instructions is an important phase for implementing an application on ...
Abstract In this paper, we propose an adaptive extensible processor in which custom instructions are...
Second Annual Reconfigurable and Adaptive Architecture Workshop (RAAW-2) : Dec. 1, 2007 : Chicago,Il...
Extensible processors allow customization for an application by extending the core instruction set a...
Abstract. Extensible processors allow customization for an application by extending the core instruc...
This paper describes an approach for adaptive dynamic instruction set extension, tuning processors t...
The relentless push in technology scaling driven by Moore's Law has witnessed fantastic gains in the...
Abstract This paper describes an approach for adaptive dynamic instruction set extension, tuning pro...
15th Annual IFIP International Conference on Very Large Scale Integration : VLSI-SoC 2007 : October ...
ABSTRACT- In this paper, we develop a heterogeneous architecture for the reconfigurable functional u...
This paper presents a reconfigurable functional unit (RFU) for an adaptive dynamic extensible proces...
A traditional extensible processor with customized circuits achieves high performance at the cost of...
In this research we investigate an approach for adaptive dynamic instruction set extension, tuning p...
To improve the performance of embedded processors, an effective technique is collapsing critical com...
To improve the performance of embedded processors, an effective technique is collapsing critical com...
Extracting appropriate custom instructions is an important phase for implementing an application on ...
Abstract In this paper, we propose an adaptive extensible processor in which custom instructions are...
Second Annual Reconfigurable and Adaptive Architecture Workshop (RAAW-2) : Dec. 1, 2007 : Chicago,Il...
Extensible processors allow customization for an application by extending the core instruction set a...
Abstract. Extensible processors allow customization for an application by extending the core instruc...
This paper describes an approach for adaptive dynamic instruction set extension, tuning processors t...
The relentless push in technology scaling driven by Moore's Law has witnessed fantastic gains in the...
Abstract This paper describes an approach for adaptive dynamic instruction set extension, tuning pro...