System-Level Techniques for Estimating and Reducing Energy Consumption in Real-Time Embedded Systems

International SoC Design Conference : October 15-16 : KoreaEnergy consumption is a fundamental barrier in taking full advantage of today and future semiconductor manufacturing technologies. We present our recent research activities and results on estimating and reducing dynamic and static energy under realtime constraints in embedded systems. This includes techniques and tools for (i) estimating instantaneous energy consumption of embedded processors during an application execution, (ii) reducing energy consumption by optimally mapping functions and data items to the scratch-pad memory (SPM), the cacheable, and noncacheable memory regions of the processor memory space, (iii) reducing the energy consumption of SPM by partitioning it into two sections with different dynamic vs. static power dissipations, (iv) reducing leakage energy in instruction cache memories by taking advantage of value-dependence of SRAM leakage due to within-die Vth variation, (v) choosing higher threshold voltage and compensating the delay-violating cache-lines by additional cache ways, and (vi) reducing energy of the logic-part of processor cores by statically implementing multiple same-ISA cores with different energy and performance characteristics