High Performance, Low Power Reconfigurable Processor for Embedded Systems

International SoC Design Conference : October 15-16 : KoreaUsing an extensible processor in which data flow graphs (DFGs) are generated from frequently executed portions (hot portions) of applications and are executed after chip-fabrication provides flexibility as well as addressing the time-to-market and significant nonrecurring engineering costs issues. In this paper, the effect of extending DFGs to control data flow graphs (CDFGs) through covering control instructions on the speedup is studied. Moreover, basic requirements for an accelerator with conditional execution support are presented. A temporal partitioning algorithm is introduced to partition the large CDFGs to smaller mappable ones under the accelerator resource constraints. To demonstrate effectiveness of the proposed ideas, they are applied to the accelerator of an extensible processor called AMBER which utilizes a matrix of functional units to accelerate the execution of the DFGs. Experimental results approve the considerable effectiveness of covering control instructions and using CDFGs versus DFGs in the aspects of performance and energy reduction