Effect of Data Prefetching on Chip Multiprocessor

複数コアを１チップに搭載するチップマルチプロセッサ(CMP)が注目されている。CMP は、複数コアで並列処理することで高い演算性能を達成することができる。しかしながら、メモリバンド幅の制約や複数コア搭載によるメモリアクセス頻度の上昇により、メモリウォール問題が深刻化する。主記憶のアクセス時間を隠蔽する方法のひとつにデータ・プリフェッチがある。CMP においてデータ・プリフェッチを行う場合、コア間の相互作用があるため、シングルコアプロセッサとは異なる効果が現れる。そこで本稿では、CMP におけるデータ・プリフェッチが性能へ与える影響を分析した。その結果、プリフェッチしたデータが無効化される割合は極めて小さく、プリフェッチを発行したコア以外のメモリアクセス時間を隠蔽するプリフェッチが約５％あることが明らかになった。Chip Multiprocessors (or CMPs) can achieve higher performance by means of exploiting thread level parallelism. Increasing the number of processor cores in a chip dramatically improves the peak performance. However, since the memory bandwidth does not scale with the number of cores, the negative impact of the memory-wall problem becomes more critical. Data prefetching is a well known approach to compensating for the poor memory performance, and has been employed in commercial processor chips. Although a number of prefetching techniques have so far been proposed, in many cases, they have assumed that the processor core in a chip is only one. In CMP chips, there are some shared resources such as L2 caches, buses, and so on. Therefore, the effect of prefetching on CMPs should be different from that on single-core processors. In this paper, we analyze the effect of prefetching on CMP performance. This paper first classifies the impact of prefetch operations issued during a program execution. Then, we discuss qualitatively and quantitatively the effect of prefetching to the memory performance. The experimental results show that the negative effect of invalidation of prefetched data is very small. In addition, it is observed that about 5％ of prefetch operations improve the cache hit rates of other cores