Dynamic Management Technique to Mitigate Performance Degradation for Low-Leakage Caches

Cool Chips X : the 10th anniversary of IEEE Symposium on Low-Power and High-Speed Chips : April 18-20, 2007 : Yokohama, JapanA number of techniques to reduce the cache leakage energy have so far been proposed. However, the low-leakage caches cause performance degradation. In order to solve this performance issue, we propose a new cache management technique. In this approach, a small number of cache lines which are frequently accessed in sleep mode are forced to stay in always-active mode. In this mode, transiting to the sleep mode is prohibited. In our evaluation, this approach can eliminate almost all performance overhead compared to conventional low-leakage cache without affecting the energy efficiency