A Cache Management Technique via Sleep-Hit Locality to Alleviate Performance Impact of Low-Leakage Caches

これまでに多くの低リーク・キャッシュが提案されてきた．しかしながら，これらの手法を用いると 待機状態ラインへの低速なアクセスが発生するため，必然的に性能が低下する．そこで本稿では低リ ーク･キャッシュにおける性能低下抑制方式として，常時活性化(always-awake)ライン方式を提案する． 具体的には，性能低下の原因となる待機状態ライン・アクセスの局所性を考慮し，アクセスが集中す るラインは常時活性化状態にする．これまでに提案されたDrowsy 方式では，15%程度の性能低下をも たらす事で84%のリーク削減率を達成した．これに対し，本稿で提案するalways-awake ラインを用い た場合，同程度のリーク削減率を維持しつつ，性能低下を8～11%に抑制することができた．A number of techniques to reduce cache leakage energy have so far been proposed. However, in these techniques, low speed accesses to a standby mode line degrade processor performance. We have analyzed the detail of cache-access behavior, and have found that there is a locality of accesses to the standby-mode lines. Based on this observation, we propose a cache management technique to alleviate the negative effect of low-leakage caches. In our approach, cache lines having high degree of sleep-hit locality are forced to stay in the high-speed but high-leakage mode. In our evaluation, it has bee observed that the Drowsy cache can achieve 84% of leakage reduction with 15% of performance degradation, while the proposed scheme worsens the performance by only 8～11% with the same degree of energy reduction of the Drowsy approach