Add to ORKGA number of techniques to reduce cache leakage have so far been proposed. However, it is not clear that 1) what kind of algorithm can be considered and 2) how much they have impact on energy and performance. To answer the questions, this paper classifies cache-leakage reduction techniques and evaluates their energy-performance efficiency. As a result, we have found that an approach employed by the Drowsy cache [1] achieves the best energy-performance efficiency with low complexity. Moreover, we investigate the potential of the approach on multi-thread program executions
Leakage power in cache memories represents a sizable fraction of total power consumption, and many t...
Abstract—With the reduction in feature size the static power component, such as the leakage power, d...
On-chip L1 and L2 caches dissipate a sizeable fraction of the total power of processors. As feature ...
Abstract- A number of techniques to reduce cache leakage have so far been proposed. However, it is n...
As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become...
We evaluate the leakage reduction for both instruction and data cache in presence of drowsy or decay...
If current technology scaling trends hold, leakage power dissipation will soon become the dominant s...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
In this paper, a technique to reduce the leakage power consumption in embedded drowsy instruction c...
4th Workshop on Optimizations for DSP and Embedded Systems : March 26, 2006 : Manhattan, New York, N...
Recently, energy dissipation by microprocessors is getting larger, which leads to a serious problem ...
Leakage energy optimization for caches has been the target of much recent effort. In this work, we f...
none4We propose a low-leakage cache architecture based on the observation of the spatio-temporal pro...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Alth...
Leakage power in cache memories represents a sizable fraction of total power consumption, and many t...
Abstract—With the reduction in feature size the static power component, such as the leakage power, d...
On-chip L1 and L2 caches dissipate a sizeable fraction of the total power of processors. As feature ...
Abstract- A number of techniques to reduce cache leakage have so far been proposed. However, it is n...
As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become...
We evaluate the leakage reduction for both instruction and data cache in presence of drowsy or decay...
If current technology scaling trends hold, leakage power dissipation will soon become the dominant s...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
In this paper, a technique to reduce the leakage power consumption in embedded drowsy instruction c...
4th Workshop on Optimizations for DSP and Embedded Systems : March 26, 2006 : Manhattan, New York, N...
Recently, energy dissipation by microprocessors is getting larger, which leads to a serious problem ...
Leakage energy optimization for caches has been the target of much recent effort. In this work, we f...
none4We propose a low-leakage cache architecture based on the observation of the spatio-temporal pro...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Alth...
Leakage power in cache memories represents a sizable fraction of total power consumption, and many t...
Abstract—With the reduction in feature size the static power component, such as the leakage power, d...
On-chip L1 and L2 caches dissipate a sizeable fraction of the total power of processors. As feature ...