In this paper, the authors discuss fine-grain power savings obtained through a technique which we call Effective Precision Matching Computation—PreMatch. It works by dynamically selecting arithmetic modules in a system designed with Functional Redundancy. Functional Redundant (FR) systems are those which contain different implementation instances of functional blocks or circuits on chip. The different instances are obtained by using different hardware algorithms and/or precision (bitwidth) of their operands. The selection of modules is completely dynamic and data-driven, i.e., it is done according to the contents of the parameters passed as input to those modules. Basically, according to the values of the operands different instances of add...
Applications in various fields, such as machine learning, scientific computing and signal/image proc...
In this paper, a 32x32-bit low power multi-precision multiplier is described, in which each building...
In this paper,we present amultiprecision (MP) reconfigurable multiplier that incorporates variable p...
Abstract — In this paper, the authors discuss fine-grain power savings obtained through a technique ...
International audienceFull-precision Floating-Point Units (FPUs) can be a source of extensive hardwa...
Modern communication systems such as 5G need high computational accuracy and dynamic range. Floating...
International audienceConnected mobile applications, known as the Internet of Things (IoT), require ...
International audienceFloating-Point (FP) computation using standard IEEE formats has a significant ...
Reconfigurable architectures promise significant performance benefits by customizing the configurati...
International audienceFor arithmetic circuits, Reduced-Precision Redundancy (RPR) is considered to b...
this paper we outline our framework for managing the dynamic precision variation. We represent the v...
Using standard Floating-Point (FP) formats for computation leads to significant hardware overhead si...
In this paper, we present a multiprecision (MP) reconfigurable multiplier that incorporates variable...
During the last decade of integrated electronic design ever more functionality has been integrated o...
This paper examines the effectiveness of employing pre-computation techniques to reduce power consum...
Applications in various fields, such as machine learning, scientific computing and signal/image proc...
In this paper, a 32x32-bit low power multi-precision multiplier is described, in which each building...
In this paper,we present amultiprecision (MP) reconfigurable multiplier that incorporates variable p...
Abstract — In this paper, the authors discuss fine-grain power savings obtained through a technique ...
International audienceFull-precision Floating-Point Units (FPUs) can be a source of extensive hardwa...
Modern communication systems such as 5G need high computational accuracy and dynamic range. Floating...
International audienceConnected mobile applications, known as the Internet of Things (IoT), require ...
International audienceFloating-Point (FP) computation using standard IEEE formats has a significant ...
Reconfigurable architectures promise significant performance benefits by customizing the configurati...
International audienceFor arithmetic circuits, Reduced-Precision Redundancy (RPR) is considered to b...
this paper we outline our framework for managing the dynamic precision variation. We represent the v...
Using standard Floating-Point (FP) formats for computation leads to significant hardware overhead si...
In this paper, we present a multiprecision (MP) reconfigurable multiplier that incorporates variable...
During the last decade of integrated electronic design ever more functionality has been integrated o...
This paper examines the effectiveness of employing pre-computation techniques to reduce power consum...
Applications in various fields, such as machine learning, scientific computing and signal/image proc...
In this paper, a 32x32-bit low power multi-precision multiplier is described, in which each building...
In this paper,we present amultiprecision (MP) reconfigurable multiplier that incorporates variable p...