Add to ORKGThis paper proposes a low-energy instruction-cache architecture, called history-based tag-comparison (HBTC) cache. The HBTC cache attempts to re-use tag-comparison results for avoiding unnecessary way activation in setassociative caches. The cache records tag-comparison results in an extended BTB, and re-uses them for directly selecting only the hit-way which includes the target instruction. In our simulation, it is observed that the HBTC cache can achieve 62% of energy reduction, with less than 1% performance degradation, compared with a conventional cache
This paper proposes a low-energy solution for CAM-based highly associative I-caches using a segmente...
Energy consumption in caches is widely studied topic. The access to a cache line consumes energy. Th...
We propose a novel energy-efficient memory architecture which relies on the use of cache with a redu...
This paper proposes a history-based tag-comparison scheme for reducing energy consumption of direct-...
ABSTRACT This paper proposes a history-based tag-comparison scheme for reducing energy consumption o...
This paper proposes an architecture for low-power direct-mapped instruction caches, called “history-...
This paper presents a novel structure for partial tag comparison cache. By triggering partial compar...
In current processors, the cache controller, which contains the cache directory and other logic such...
Abstract: Caches contribute to much of a microprocessor system's set-associative cache. However...
[[abstract]]Conventional set‐associative caches, with higher associativity, provide lower miss rates...
Caches contribute to much of a microprocessor system's power and energy consumption. We have de...
SUMMARY Energy consumption has become an important design consideration in modern processors. Theref...
Due to performance reasons, all ways in set-associative level-one (L1) data caches are accessed in p...
On-chip caches have been playing an important role in achieving high performance processors. In part...
Abstract—Due to performance reasons, all ways in set-associative level-one (L1) data caches are acce...
This paper proposes a low-energy solution for CAM-based highly associative I-caches using a segmente...
Energy consumption in caches is widely studied topic. The access to a cache line consumes energy. Th...
We propose a novel energy-efficient memory architecture which relies on the use of cache with a redu...
This paper proposes a history-based tag-comparison scheme for reducing energy consumption of direct-...
ABSTRACT This paper proposes a history-based tag-comparison scheme for reducing energy consumption o...
This paper proposes an architecture for low-power direct-mapped instruction caches, called “history-...
This paper presents a novel structure for partial tag comparison cache. By triggering partial compar...
In current processors, the cache controller, which contains the cache directory and other logic such...
Abstract: Caches contribute to much of a microprocessor system's set-associative cache. However...
[[abstract]]Conventional set‐associative caches, with higher associativity, provide lower miss rates...
Caches contribute to much of a microprocessor system's power and energy consumption. We have de...
SUMMARY Energy consumption has become an important design consideration in modern processors. Theref...
Due to performance reasons, all ways in set-associative level-one (L1) data caches are accessed in p...
On-chip caches have been playing an important role in achieving high performance processors. In part...
Abstract—Due to performance reasons, all ways in set-associative level-one (L1) data caches are acce...
This paper proposes a low-energy solution for CAM-based highly associative I-caches using a segmente...
Energy consumption in caches is widely studied topic. The access to a cache line consumes energy. Th...
We propose a novel energy-efficient memory architecture which relies on the use of cache with a redu...