Add to ORKGThis paper proposes a history-based tag-comparison scheme for reducing energy consumption of direct-mapped instruction caches. The proposed cache efficiently exploits programexecution footprints recorded in the Branch Target Buffer (BTB), and attempts to detect and eliminate unnecessary tag checks at run time. Simulation results show that our approach can eliminate up to 95% of tag checks, saving the cache energy by 17%, while affecting the processor performance by only 0.2%
Abstract: Caches contribute to much of a microprocessor system's set-associative cache. However...
[EN] Power consumption in current high-performance chip multiprocessors (CMPs) has become a major de...
Low-power research has flourished recently, in an attempt to address packaging and cooling concerns ...
ABSTRACT This paper proposes a history-based tag-comparison scheme for reducing energy consumption o...
This paper proposes an architecture for low-power direct-mapped instruction caches, called “history-...
This paper proposes a low-energy instruction-cache architecture, called history-based tag-comparison...
In this paper we present a software-directed customization method-ology for minimizing the energy di...
SUMMARY Energy consumption has become an important design consideration in modern processors. Theref...
On-chip caches have been playing an important role in achieving high performance processors. In part...
In current processors, the cache controller, which contains the cache directory and other logic such...
Energy consumption in caches is widely studied topic. The access to a cache line consumes energy. Th...
We propose a novel energy-efficient memory architecture which relies on the use of cache with a redu...
The instruction cache is a critical component in any microprocessor. It must have high performance t...
This paper proposes a low-energy solution for CAM-based highly associative I-caches using a segmente...
The number of battery powered devices is growing significantly and these devices require energy-effi...
Abstract: Caches contribute to much of a microprocessor system's set-associative cache. However...
[EN] Power consumption in current high-performance chip multiprocessors (CMPs) has become a major de...
Low-power research has flourished recently, in an attempt to address packaging and cooling concerns ...
ABSTRACT This paper proposes a history-based tag-comparison scheme for reducing energy consumption o...
This paper proposes an architecture for low-power direct-mapped instruction caches, called “history-...
This paper proposes a low-energy instruction-cache architecture, called history-based tag-comparison...
In this paper we present a software-directed customization method-ology for minimizing the energy di...
SUMMARY Energy consumption has become an important design consideration in modern processors. Theref...
On-chip caches have been playing an important role in achieving high performance processors. In part...
In current processors, the cache controller, which contains the cache directory and other logic such...
Energy consumption in caches is widely studied topic. The access to a cache line consumes energy. Th...
We propose a novel energy-efficient memory architecture which relies on the use of cache with a redu...
The instruction cache is a critical component in any microprocessor. It must have high performance t...
This paper proposes a low-energy solution for CAM-based highly associative I-caches using a segmente...
The number of battery powered devices is growing significantly and these devices require energy-effi...
Abstract: Caches contribute to much of a microprocessor system's set-associative cache. However...
[EN] Power consumption in current high-performance chip multiprocessors (CMPs) has become a major de...
Low-power research has flourished recently, in an attempt to address packaging and cooling concerns ...