This paper presents a new concept called active data bitwidth, which is the effective data length of data bus. By means of profiling the active data bitwidth dynamically, we present a novel low-energy memory access technique for on-chip data memory design. By reducing the redundant access energy of data memory, our experimental results of two real applications, show that we can achieve significant energy reduction. Compared to the monolithic memory, for JPEG, 52.2%; for MPEG-2 84.2%, the energy reduction is reported. Compared to the memory banking technique, 12.3% energy reduction for JPEG and 65.9% for MPEG-2 is reported
Memory-intensive operations and their memory access latency are often the performance bottleneck in ...
Main memory is responsible for a significant fraction of the energy consumed by servers. Prior work ...
Advances in DRAM technology have led many researchers to integrate computational logic on DRAM chips...
This paper presents a new concept called active data bitwidth, which is the effective data length of...
This paper presents a novel low-energy memory design technique, considering effective bitwidth of va...
Abstract: Static energy dissipation in cache memories will constitute an increasingly larger portion...
The need in low power processor design is growing due to the reliability problem for high frequency,...
Most memory devices store and retrieve data by addressing specific memory locations. As a result, th...
Data movement over long and highly capacitive inter-connects is responsible for a large fraction of ...
To transfer a small number, we inherently need a small number of bits. However all bit lines on a da...
<p>Phase Change Memory (PCM) is a promising alternative to DRAM to achieve high memory capacity at l...
Graphics Processing Units (GPUs) and other throughput processing architectures have scaled performan...
In embedded system design, the designer has to choose an onchip memory configuration that is suitabl...
Abstract External buses consume substantial power for their high capacitances of bus lines and I/O p...
With the fast increase of the transistors these years, the power consumption of the IC chip also inc...
Memory-intensive operations and their memory access latency are often the performance bottleneck in ...
Main memory is responsible for a significant fraction of the energy consumed by servers. Prior work ...
Advances in DRAM technology have led many researchers to integrate computational logic on DRAM chips...
This paper presents a new concept called active data bitwidth, which is the effective data length of...
This paper presents a novel low-energy memory design technique, considering effective bitwidth of va...
Abstract: Static energy dissipation in cache memories will constitute an increasingly larger portion...
The need in low power processor design is growing due to the reliability problem for high frequency,...
Most memory devices store and retrieve data by addressing specific memory locations. As a result, th...
Data movement over long and highly capacitive inter-connects is responsible for a large fraction of ...
To transfer a small number, we inherently need a small number of bits. However all bit lines on a da...
<p>Phase Change Memory (PCM) is a promising alternative to DRAM to achieve high memory capacity at l...
Graphics Processing Units (GPUs) and other throughput processing architectures have scaled performan...
In embedded system design, the designer has to choose an onchip memory configuration that is suitabl...
Abstract External buses consume substantial power for their high capacitances of bus lines and I/O p...
With the fast increase of the transistors these years, the power consumption of the IC chip also inc...
Memory-intensive operations and their memory access latency are often the performance bottleneck in ...
Main memory is responsible for a significant fraction of the energy consumed by servers. Prior work ...
Advances in DRAM technology have led many researchers to integrate computational logic on DRAM chips...