Limits of Parallelism on Thread-Level Speculative Parallel Processing Architecture

International Workshop on Informationons and Electrical Engineering (IWIE2002)Two fundamental restrictions that limit the amount of instructionlevel parallelism extracted from sequential programs are control flow and data flow. TLSP (Thread-Level Speculative Parallel processing) architecture gains high parallelism using three techniques (speculation with branch prediction, control dependence analysis, executing multiple flows of control) which relax constraints due to control dependences. In this paper, we evaluate the effects of three techniques (memory disambiguation, renaming, value prediction) which relax constraints due to data dependences on TLSP architecture. We have two major results. First, parallelism for TLSP architecture is restricted by enormous output and anti dependences on memory. Second, value prediciton has large effects on TLSP architecture