LUT saving in embedded FPGAs for cache locking in real-time systems

[EN] In recent years, cache locking have appeared as a solution to ease the schedulability analysis of real-time systems using cache memories maintaining, at the same time, similar performance improvements than regular cache memories. New devices for the embedded market couple a processor and a programmable logic device designed to enhance system flexibility and increase the possibilities of customisation in the field. This arrangement may help to improve the use of cache locking in real-time systems. This work proposes the use of this embedded programmable logic device to implement a logic function that provides the cache controller the information it needs in order to determine if a referenced main memory block has to be loaded and locked into the cache; we have called this circuit a Locking State Generator. Experiments show the requirements in terms of number of hardware resources and a way to reduce them and the circuit complexity. This reduction ranges from 50% up to 80% of the number of hardware resources originally needed to build the Locking State Generator circuit.This work has been partially supported by PAID-06-11/2055 of Universitat Politecnica de València and TIN2011-28435- C03-01 of Ministerio de Ciencia e Innovacion.Martí Campoy, A.; Rodríguez Ballester, F.; Ors Carot, R. (2013). LUT saving in embedded FPGAs for cache locking in real-time systems. International Journal On Advances in Systems and Measurements. 6(1-2):190-199. http://hdl.handle.net/10251/46758S19019961-