Optimization of Fault-Insertion Test and Diagnosis of Functional Failures

<p>Advances in semiconductor technology and design automation methods have introduced a new era for electronic products. With design sizes in millions of logic gates and operating frequencies in GHz, defects-per-million rates continue to increase, and defects are manifesting themselves in subtle ways. Traditional test methods are not sufficient to guarantee product quality and diagnostic programs cannot rapidly locate the root cause of failure in large systems. Therefore, there is a need for efficient fault diagnosis methods that can provide quality assurance, accelerate new product release, reduce manufacturing cost, and increase product yield.</p><p>This thesis research is focused on fault-insertion test (FIT) and fault diagnosis at the board and system levels. FIT is a promising technique to evaluate system reliability and facilitate fault diagnosis. The error-handling mechanism and system reliability can be assessed in the presence of intentionally inserted faults, and artificial faulty scenarios can be used as references for fault diagnosis. However, FIT needs to be deployed under constraints of silicon area, design effort, availability of equipment, and what is actually possible to test from one design to the next. In this research, physical defect modeling is developed to provide an efficient solution for fault-insertion test. Artificial faults at the pin level are created to represent physical defects inside devices. One pin-level fault is able to mimic the erroneous behaviors caused by multiple internal defects. Therefore, system reliability can be evaluated in a more efficient way.</p><p>Fault diagnosis is a major concern in the semiconductor industry. As the density and complexity of systems increase relentlessly and the subtle effects of defects in nanometer technologies become more pronounced, fault diagnosis becomes difficult, time-consuming, and ineffective. Diagnosis of functional failure is especially challenging. Moreover, the cost associated with board-level diagnosis is escalating rapidly. Therefore, this thesis presents a multi-pronged approach to improve the efficiency and accuracy of fault diagnosis, including the construction of a diagnostic framework with FIT and Bayesian inference, the extraction of an effective fault syndrome (error flow), the selection of diagnosis-oriented fault-insertion points, and the application of machine learning for intelligent diagnosis.</p><p>First, in the inference-based diagnosis framework, FIT is used to create a large number of faulty samples and derive the probabilities needed for the application of Bayes' theorem; next the probability of a fault candidate being the root cause can be inferred based on the given fault syndromes. Results on a case study using an open-source RISC system-on-chip demonstrate the feasibility and effectiveness of the proposed approach. Second, the concept of error flow is proposed to mimic actual data propagation in a circuit, and thus it reflects the logic functionality and timing behavior of circuits. With this additional information, more fault syndromes are distinguishable. Third, diagnosis-oriented fault-insertion points are defined and selected to create the representative and distinguishable syndromes. Finally, machine learning approaches are used to facilitate the debug and repair process. Without requiring the need to understand the complex functionality of the boards, an intelligent diagnostic system is designed to automatically exploit the diagnostic knowledge available from past cases and make decisions on new cases.</p><p>In summary, this research has investigated efficient means to perform fault-insertion test and developed automated and intelligent diagnosis methods targeting functional failures at the board level. For a complex circuit board currently in production, the first-time success rate for diagnosis has been increased from 35.63% to 72.64%. It is expected to contribute to quality assurance, product release acceleration, and manufacturing-cost reduction in the semiconductor industry.</p>Dissertatio