We propose UNITD, a unified hardware coherence framework that integrates translation coherence into the existing cache coherence protocol. In UNITD coherence protocols, the TLBs participate in the cache coherence protocol just like the instruction and data caches, without requiring any changes to the existing coherence protocol. UNITD eliminates the need for the software TLB shootdown routine, a procedure known to be performance costly and non-scalable. We evaluate snooping and directory UNITD coherence protocols on multicore processors with 2-16 cores, and we demonstrate that UNITD reduces the performance penalty associated with TLB coherence to almost zero. ©2009 IEEE
Cache coherence protocols limit the scalability of multicore and manycore architectures and are resp...
System-on-a-chip (SoC) designs is characterized by heavy reuse of IP blocks to satisfy specific comp...
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Comput...
Many future shared-memory multiprocessor servers will both target commercial workloads and use highl...
International audienceMany multicore and manycore architectures support hardware cache coherence. Ho...
Both hardware-controlled and compiler-directed mechanisms have been proposed for maintaining cache c...
DASH is a scalable shared-memory multiprocessor currently being developed at Stanford’s Computer Sys...
In large scale machines, thousands of processor cycles, in other words, missed opportunities to issu...
New generation System-on-Chips will be extremely complex devices, composed from complex subsystems, ...
Emerging multiprocessor architectures such as chip multiprocessors, embedded architectures, and mas...
AbstractDirectory-based cache coherency is commonly accepted as the design of choice to provide high...
As the number of cores increases on chip multiprocessors, coherence is fast becoming a central issue...
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cac...
[[abstract]]A cache coherence protocol for a multiprocessor system. Each processor in the system has...
Abstract. User-controllable coherence revives the idea of cooperation between software and hardware ...
Cache coherence protocols limit the scalability of multicore and manycore architectures and are resp...
System-on-a-chip (SoC) designs is characterized by heavy reuse of IP blocks to satisfy specific comp...
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Comput...
Many future shared-memory multiprocessor servers will both target commercial workloads and use highl...
International audienceMany multicore and manycore architectures support hardware cache coherence. Ho...
Both hardware-controlled and compiler-directed mechanisms have been proposed for maintaining cache c...
DASH is a scalable shared-memory multiprocessor currently being developed at Stanford’s Computer Sys...
In large scale machines, thousands of processor cycles, in other words, missed opportunities to issu...
New generation System-on-Chips will be extremely complex devices, composed from complex subsystems, ...
Emerging multiprocessor architectures such as chip multiprocessors, embedded architectures, and mas...
AbstractDirectory-based cache coherency is commonly accepted as the design of choice to provide high...
As the number of cores increases on chip multiprocessors, coherence is fast becoming a central issue...
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cac...
[[abstract]]A cache coherence protocol for a multiprocessor system. Each processor in the system has...
Abstract. User-controllable coherence revives the idea of cooperation between software and hardware ...
Cache coherence protocols limit the scalability of multicore and manycore architectures and are resp...
System-on-a-chip (SoC) designs is characterized by heavy reuse of IP blocks to satisfy specific comp...
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Comput...