Explicit communication and synchronization in SARC

[EN] A new network interface optimized for SARC supports synchronization and explicit communication and provides a robust mechanism for event responses. Full-system simulation of the authors' design achieved a 10- to 40-percent speed increase over traditional cache architectures on 64 cores, a two- to four-fold decrease in on-chip network traffic, and a three- to five-fold decrease in lock and barrier latency.This work is supported by the European Commission in the context of the projects SARC (FP6 IP #27648), Unisix (Marie-Curie #509595), and the HiPEAC Network of Excellence (NoE 004408). We also thank, for their assistance in designing the architecture and their collaboration in the SARC project, Alex Ramirez, Georgi Gaydadjiev, Angelos Bilas, George Kalokerinos, George Nikiforos, Dimitris Tsaliagos, Xiaojun Yang, Spyros Lyberis, Christos Sotiriou, and Michael Ligerakis.Katevenis, MG.; Papaefstathiou, V.; Kavadias, S.; Pnevmatikatos, D.; Nikolopoulos, DS.; Silla Jiménez, F. (2010). Explicit communication and synchronization in SARC. IEEE Micro. 30(5):30-41. doi:10.1109/MM.2010.77S304130