Add to ORKGAn equalization circuit is presented that reduces data-dependent jitter by aligning data transition deviations. This paper presents an analytic solution to data-dependent jitter and demonstrates its impact on the phase noise of the recovered clock. A data-dependent jitter equalizer is presented that compensates for impairment of the channel and lowers the phase noise of the recovered clock. The circuit is implemented in a SiGe BiCMOS process and operates at 10 Gb/s. It suppresses phase noise resulting from data-dependent jitter by 10 dB
In this paper, we presents a programmable jitter generator. Different from the traditional jitter ge...
Timing jitter is a concern in high frequency timing circuits. Its presence can degrade system perfor...
In this paper we present an on-chip clock jitter digital measurement scheme for high performance mic...
An equalization circuit is presented that reduces data-dependent jitter by aligning data transition ...
An equalization circuit is presented that reduces data-dependent jitter by aligning data transition ...
Abstract—Data-dependent jitter limits the bit-error rate (BER) performance of broadband communicatio...
A novel jitter equalization circuit is presented that addresses crosstalk-induced jitter in high-spe...
This thesis describes three contributions in the area of on-chip jitter measurement and characteriza...
A novel jitter equalization circuit is presented that addresses crosstalk-induced jitter in high-spe...
This work focused on high-speed source-synchronous clock and multi-channel data receivers for inter-...
The impact of gating timing jitter on a 160Gb/s demultiplexer is investigated by using two pulse sou...
120 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2004.In addition to ISI, jitter al...
The paper describes a novel method for simple estimation of jitter contained in a received digital s...
This paper presents a jitter reduction technique utilized in a cyclic injection DLL clock generator ...
Abstract: – It is know for quite some time now (cf. [1-3] and [4]) that practical alias-free signal...
In this paper, we presents a programmable jitter generator. Different from the traditional jitter ge...
Timing jitter is a concern in high frequency timing circuits. Its presence can degrade system perfor...
In this paper we present an on-chip clock jitter digital measurement scheme for high performance mic...
An equalization circuit is presented that reduces data-dependent jitter by aligning data transition ...
An equalization circuit is presented that reduces data-dependent jitter by aligning data transition ...
Abstract—Data-dependent jitter limits the bit-error rate (BER) performance of broadband communicatio...
A novel jitter equalization circuit is presented that addresses crosstalk-induced jitter in high-spe...
This thesis describes three contributions in the area of on-chip jitter measurement and characteriza...
A novel jitter equalization circuit is presented that addresses crosstalk-induced jitter in high-spe...
This work focused on high-speed source-synchronous clock and multi-channel data receivers for inter-...
The impact of gating timing jitter on a 160Gb/s demultiplexer is investigated by using two pulse sou...
120 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2004.In addition to ISI, jitter al...
The paper describes a novel method for simple estimation of jitter contained in a received digital s...
This paper presents a jitter reduction technique utilized in a cyclic injection DLL clock generator ...
Abstract: – It is know for quite some time now (cf. [1-3] and [4]) that practical alias-free signal...
In this paper, we presents a programmable jitter generator. Different from the traditional jitter ge...
Timing jitter is a concern in high frequency timing circuits. Its presence can degrade system perfor...
In this paper we present an on-chip clock jitter digital measurement scheme for high performance mic...