1.5 Gb/s, 6.6 mW 8-bit multiplexer using two-phase dynamic FET logic

GaAs Two-Phase Dynamic FET Logic (TDFL) gates are used in the design of a high-speed, low-power 8-bit multiplexer. Operation of the multiplexer is demonstrated at 1.5 Gb/s with an associated power dissipation of 6.6 mW. The operation of the multiplexer demonstrates the high equivalent gate count of TDFL gates, direct compatibility between TDFL and Direct-Coupled FET Logic (DCFL), and the advantages of shift register architectures when simple, low-power dynamic latches are available in GaAs circuits