An FPGA implementation of a Feed-Back Chaotic Synchronization for secure communications

In this paper, we propose a hardware implementation of a Feed-Back Chaotic Synchronization (FCS) for designing a real-time secure symmetric encryption scheme. This proposed scheme allows for the design and implementation of real time synchronization between two embedded chaotic generators for secure communications. The implementation and experimental results mapped on two Xilinx FPGA Virtex technology platforms using two Lorenz three-dimensional continuous chaotic systems demonstrate the feasibility and the usefulness of this synchronization approach in terms of performance and hardware resources for embedded encryption systems