Metastability causes unpredictable behavior in circuits, and can cause circuit failure. Any binary valued circuit element that holds state is vulnerable to metastability. Although the possibility of metastability cannot be completely eliminated in a circuit, the goal is to reduce it as much as possible. In this thesis, we discuss the design of a latch that effectively reduces metastability in circuits. In today’s SoC designs, different clock domains are often used for different functional units. If the clock domains are not synchronous, synchronizers are required for data crossing clock domains. A traditional synchronizer consists of 2 regular flip- flops and is not suited for high frequency operation. In this thesis, we present a new syn...
International audienceIn classical synchronous designs, supply voltage droops can be handled by acco...
Abstract--- In this paper, we will illustrate the mechanism of metastability issues in ASICs designs...
Abstract—The periodic nature of the global clock in traditional synchronous designs forces circuits ...
Communication across unsynchronized clock domains is inherently vulnerable to metastable upsets; no ...
In this paper, we use circuit simulations to characterize the effects of technology scaling on the m...
Synchronizers are used at the clock domain crossings and at asynchronous interfaces to reduce the pr...
Technology scaling has paved way for complex systems such as heterogeneous multi core processors, co...
Upset hardened dual-interlocked cell (DICE) [1] has found an important place in circuits for space a...
This paper presents a detailed analysis of metastable behavior in CMOS Current Mode Logic (CML) latc...
Graduation date: 1983The problem of synchronization arises in the interaction among\ud digital syste...
Razor-based circuits can run faster or at a lower voltage than those designed to work at the worst c...
Designing synchronous sequential circuits consisting of clocked storage elements such as flip-flops ...
Error containment is an important concept in fault tolerant system design, and techniques like votin...
Abstract — Synchronizers play a key role in multi-clock domains systems on chip and their performanc...
Melchiorre, Robert, "A study of metastability in CMOS latches " (1992). Theses and Dissert...
International audienceIn classical synchronous designs, supply voltage droops can be handled by acco...
Abstract--- In this paper, we will illustrate the mechanism of metastability issues in ASICs designs...
Abstract—The periodic nature of the global clock in traditional synchronous designs forces circuits ...
Communication across unsynchronized clock domains is inherently vulnerable to metastable upsets; no ...
In this paper, we use circuit simulations to characterize the effects of technology scaling on the m...
Synchronizers are used at the clock domain crossings and at asynchronous interfaces to reduce the pr...
Technology scaling has paved way for complex systems such as heterogeneous multi core processors, co...
Upset hardened dual-interlocked cell (DICE) [1] has found an important place in circuits for space a...
This paper presents a detailed analysis of metastable behavior in CMOS Current Mode Logic (CML) latc...
Graduation date: 1983The problem of synchronization arises in the interaction among\ud digital syste...
Razor-based circuits can run faster or at a lower voltage than those designed to work at the worst c...
Designing synchronous sequential circuits consisting of clocked storage elements such as flip-flops ...
Error containment is an important concept in fault tolerant system design, and techniques like votin...
Abstract — Synchronizers play a key role in multi-clock domains systems on chip and their performanc...
Melchiorre, Robert, "A study of metastability in CMOS latches " (1992). Theses and Dissert...
International audienceIn classical synchronous designs, supply voltage droops can be handled by acco...
Abstract--- In this paper, we will illustrate the mechanism of metastability issues in ASICs designs...
Abstract—The periodic nature of the global clock in traditional synchronous designs forces circuits ...