Gathering Memory Hierarchy Statistics in QEMU

International audienceFast functional verification using Transaction Level Modeling of hardware/software systems typically makes use of fast, dynamic binary translation based, processor models. When it comes to estimating performance figures, either higher level analytical models, or lower level cycle-accurate/approximate models are generally used. However, we believe that metrics relative to the memory hierarchy can be relatively accurately acquired while working with fast processor simulators at transaction level. This, of course, sacrifices some speed for accuracy, but lets the designer work in their usual environment and the resulting model only sacrifices about 30% in terms of performance, for a single core model. In this paper, we detail our level one cache modeling strategy and how we implement it. We then measure simulation speed overheads and compare our statistics with information gathered on the Cortex R5 PMU of Xilinx UltraScale-Plus board running the same benchmark