The speed gap between CPU and memory is impairing performance. Cache compression and hardware prefetching are two techniques that could confront this bottleneck by decreasing last level cache misses. However, compression and prefetching have positive interactions, as prefetching benefits from higher cache capacity and compression increases the effective cache size. This study proposes Compressed cache Layout Aware Prefetching (CLAP) to leverage the recently proposed sector-based compressed cache layouts, such as SCC or YACC, to create a synergy between compressed caches and prefetching. The idea of this approach is to prefetch contiguous blocks that can be compressed and co-allocated together with the requested block on a miss access. Prefe...
As the trends of process scaling make memory system even more crucial bottleneck, the importance of ...
With off-chip memory access taking 100's of processor cycles, getting data to the processor in a tim...
International audienceHardware cache compression derives from software-compression research; yet, it...
The speed gap between CPU and memory is impairing performance. Cache compression and hardware prefet...
Abstract—Cache compression improves the performance of a multi-core system by being able to store mo...
International audienceRecent advances in research on compressed caches make them an attractive desig...
Processors face steep penalties when accessing on-chip memory in the form of high latency. On-chip c...
Data prefetching is an effective way to bridge the increasing performance gap between processor and ...
This thesis focuses on addressing interference at the shared memory-hierarchy resources: last level ...
The gap between processor and memory speed appears as a serious bottleneck in improving the performa...
Cache memories play a critical role in bridging the latency, bandwidth, and energy gaps between core...
The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xp...
In this dissertation, we provide hardware solutions to increase the efficiency of the cache hierarch...
International audienceThe effectiveness of a compressed cache depends on three features: i) th...
Projections of computer technology forecast proces-sors with peak performance of 1,000 MIPS in the r...
As the trends of process scaling make memory system even more crucial bottleneck, the importance of ...
With off-chip memory access taking 100's of processor cycles, getting data to the processor in a tim...
International audienceHardware cache compression derives from software-compression research; yet, it...
The speed gap between CPU and memory is impairing performance. Cache compression and hardware prefet...
Abstract—Cache compression improves the performance of a multi-core system by being able to store mo...
International audienceRecent advances in research on compressed caches make them an attractive desig...
Processors face steep penalties when accessing on-chip memory in the form of high latency. On-chip c...
Data prefetching is an effective way to bridge the increasing performance gap between processor and ...
This thesis focuses on addressing interference at the shared memory-hierarchy resources: last level ...
The gap between processor and memory speed appears as a serious bottleneck in improving the performa...
Cache memories play a critical role in bridging the latency, bandwidth, and energy gaps between core...
The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xp...
In this dissertation, we provide hardware solutions to increase the efficiency of the cache hierarch...
International audienceThe effectiveness of a compressed cache depends on three features: i) th...
Projections of computer technology forecast proces-sors with peak performance of 1,000 MIPS in the r...
As the trends of process scaling make memory system even more crucial bottleneck, the importance of ...
With off-chip memory access taking 100's of processor cycles, getting data to the processor in a tim...
International audienceHardware cache compression derives from software-compression research; yet, it...