Study of Si(100)-SiO2 Interface Trap Time Constant Distributions in Large Area Conventional MOSFETs-Comparison with Submicron Devices

International audiencePb0 centers are the main defects at the Si(100)/SiO2 interface in conventional MOS transistors. Besides, the charge pumping (CP) technique in which a MOSFET is repeatedly switched between inversion and accumulation has been widely used for studying single capture/emission events in deep submicron transistors. In CP, the minority carriers stored into interface traps in inversion recombine in accumulation with majority carriers from the substrate (n-channel case). This provides a CP current which can be studied. When it was accepted that in submicron MOSFETs the CP current was given by Icp = f.q.N, where f is the gate signal frequency, q the electron charge, N the number of traps entering Icp, recently, Tsuchiya and co-workers, pointed out steps heights equal to 2.q: Pb0 centers with their donor-like and acceptor-like states in the lower and upper halves of the silicon bandgap, respectively were therefore measured for the first time in submicron devices. In the present paper, the traps remaining electrically active at the Si(100)-SiO2 interface in large area conventional MOSFETs after the full technological process including forming gas annealing are studied. This is achieved using techniques developed in recent years that use the variation of the gate signal frequency for different gate voltage swings. The trap time constant distributions that exist at this interface are studied as function of gate voltage and gate signal frequency. The results are discussed with regard to the CP models previously proposed and to CP curves simulation