This paper presents the implementation of a high speed low power over sampled CMOS comparator for use in a reconfigurable Flash Analog to Digital Converter (ADC) as part of a Direct Sequence - Spread Spectrum (DS-SS) based Ultra Wide Band (UWB) Radio receiver. The comparator was designed using a 90 nanometre (nm) CMOS technology process. The switching speed of the comparator is 4 giga-samples per second (GSps) for a 528 megahertz (MHz) input bandwidth. The comparator operates on a 1V power supply. The total input referred offset of the comparator at 4 GSps is 33.1 mV which is about 0.6 LSB for a 4 bit flash converter
We present a 4-bit power scalable flash analog-to-digital converter in digital 0.18-mum CMOS, target...
With higher-level integration driven by increasingly complex digital systems and downscaling CMOS pr...
Abstract — The continued speed improvement of serial links and appearance of new communication techn...
This paper presents a design of high-speed flash analog-to-digital converter (ADC) in 0.13-μm CMOS t...
This paper presents a design of high-speed flash analog-to-digital converter (ADC) in 0.13-μm CMOS t...
This paper presents a design of high-speed flash analog-to-digital converter (ADC) in 0.13-μm CMOS t...
This paper presents a design of high-speed flash analog-to-digital converter (ADC) in 0.13-μm CMOS t...
Over the past few years Ultra Wide Band (UWB) technology has taken the realms of communications circ...
The fast development of the Digital Integrated Circuit (IC) techniques has promoted the trend to pro...
This paper presents the design of a comparator with low power, low offset voltage, high resolution, ...
A 2.5 GS/s flash ADC, fabricated in 90nm CMOS utilizes comparator redundancy to avoid traditional po...
This thesis describes research on very-high-sampling-rate, moderate-resolution, CMOS, analog-to-digi...
This thesis describes research on very-high-sampling-rate, moderate-resolution, CMOS, analog-to-digi...
This paper presents a design of a high speed Comparator design using 65nm digital CMOS technology on...
Abstract--Dynamic comparators with high speed, low power and low offset voltage are the main prerequ...
We present a 4-bit power scalable flash analog-to-digital converter in digital 0.18-mum CMOS, target...
With higher-level integration driven by increasingly complex digital systems and downscaling CMOS pr...
Abstract — The continued speed improvement of serial links and appearance of new communication techn...
This paper presents a design of high-speed flash analog-to-digital converter (ADC) in 0.13-μm CMOS t...
This paper presents a design of high-speed flash analog-to-digital converter (ADC) in 0.13-μm CMOS t...
This paper presents a design of high-speed flash analog-to-digital converter (ADC) in 0.13-μm CMOS t...
This paper presents a design of high-speed flash analog-to-digital converter (ADC) in 0.13-μm CMOS t...
Over the past few years Ultra Wide Band (UWB) technology has taken the realms of communications circ...
The fast development of the Digital Integrated Circuit (IC) techniques has promoted the trend to pro...
This paper presents the design of a comparator with low power, low offset voltage, high resolution, ...
A 2.5 GS/s flash ADC, fabricated in 90nm CMOS utilizes comparator redundancy to avoid traditional po...
This thesis describes research on very-high-sampling-rate, moderate-resolution, CMOS, analog-to-digi...
This thesis describes research on very-high-sampling-rate, moderate-resolution, CMOS, analog-to-digi...
This paper presents a design of a high speed Comparator design using 65nm digital CMOS technology on...
Abstract--Dynamic comparators with high speed, low power and low offset voltage are the main prerequ...
We present a 4-bit power scalable flash analog-to-digital converter in digital 0.18-mum CMOS, target...
With higher-level integration driven by increasingly complex digital systems and downscaling CMOS pr...
Abstract — The continued speed improvement of serial links and appearance of new communication techn...