A high throughput low power compact AES s-box implementation using composite field arithmetic and algebraic normal form representation

In this work, our aim is to achieve a high throughput compact AES S-box with minimal power consumption. In most VLSI implementations, there exist a definite trade off between hardware performance and its operating requirements. In this work, we propose a novel pipelining arrangement over the compact composite field AES S-box such that both high throughput and low power are optimized. Our S-box outperformed the conventional pipelined AES S-box from three perspectives, (i) the most optimum (compact and short critical path) composite field AES S-box is used, which has different arithmetic properties compared to previous works; (ii) Algebraic Normal Form (ANF) representation is utilized to induce consistent and optimal pipelining arrangement; and (iii) Fine-grain pipelining is applied in the GF (24) multiplier. As such, a higher throughput rate is attained and at the same time the dynamic hazards is mitigated. A high throughput of 3.3 Gbps with a low power consumption of 34.98 mW and total of 95 LE (Logic Element) composite field AES S-box is reported in this work