Process Variation-Aware Timing Optimization with Load Balance of Multiple Paths in Dynamic and Mixed-Static-Dynamic CMOS Logic

The semiconductor technology has been advancing rapidly over the past decade to result in the design of several innovative applications. This advancement of technology with the shrinking device has allowed for placement of billions of transistor on a single microprocessor chip. On the other hand, this shrinking device sizes has presented the design engineers with two major challenges: timing optimization at multiple giga-hertz frequencies, and reducing the daunting effects of semiconductor process variations. Failure to account for these process variations often results in loss of design productivity by one generation, and might even result in design failure. This research presents two timing optimization algorithms while accounting for process variations. The process variation-aware Load Balance of Multiple Paths (LBMP) algorithm is designed for timing optimization of dynamic CMOS circuits. Implemented on several dynamic CMOS circuits, the LBMP algorithm has demonstrated an average reduction in delay, uncertainty, and sensitivity from process variations by 48%, 57% and 14% respectively. The process variation-aware Path Oriented IN Time (POINT) optimization flow for mixed-static-dynamic CMOS circuits partitions a design based on critical paths, chooses effective circuit style, and performs switch level timing optimization using the LBMP algorithm. Verified through implementation on several standard benchmark circuits, the POINT optimization flow has demonstrated an average reduction in delay and uncertainty from process variations by 17% and 13% over state-of-the-art commercial optimization tools