Methods for Trustworthy Design of On-Chip Bus Interconnect for General-Purpose Processors

Military electronics rely on commodity processors, many of which are manufactured overseas where the trustworthiness of the foundries is uncertain. This thesis attempts to answer the question of whether common bus protocols in use today differ significantly with respect to security, by conducting an analysis of common integrated circuit bus protocols (Inter-Integrated Circuit [I2C], Advanced Microcontroller Bus Architecture [AMBA], HyperTransport, Wishbone, and CoreConnect) based on the Flaw Hypothesis Methodology (FHM). This thesis follows the four stages of FHM. The first stage is Flaw Generation, which involves creating hypothetical attack scenarios. The next is Flaw Confirmation, which involves confirming the flaws generated in the first stage through analysis of the specifications of the bus architectures as well as testing and research in the literature. The third stage is Flaw Generalization, which evaluates the impact of each flaw to determine whether it suggests that a more serious flaw exists in that bus architecture. The final stage is Flaw Elimination, which identifies strategies (and their costs) for mitigating the vulnerabilities based on techniques in the hardware security literature. We conclude that the bus architectures we analyzed differ significantly with respect to security.http://archive.org/details/methodsfortrustw109456790Lieutenant Commander, United States Nav