Konzeption und Entwurf flächen- und energie-effizienter digitaler GNSS-Empfänger

Since the intentional degradation of the US-American Navstar-GPS signal has been switched off in the year 2000 and thanks to the progress in the integration of digital and analog circuits the usage of satellite navigation receivers has been increased significantly. Beside the "Navstar GPS" system, which is supported by most commercially receivers available today, further satellite navigation systems already exist or are under current development. The Russian system "GLONASS" is fully operable again since 2009 and the European "Galileo" as well as the Chinese "Compass" systems are in the deployment phase. A full constellation, consisting of these four "Global Navigation Satellite Systems" (GNSSs), will significantly increase accuracy, availability, and integrity for future GNSS users. Therefore, this thesis focuses on the conception and design of energy- and area-efficient digital GNSS receivers. A new methodology is developed for a structured analysis of GNSS receiver architectures and receiver parameters, which identifies efficient receiver solutions for a given application. The presented approach comprises optimizations on all levels of CMOS design, starting from algorithmic system level and ending with the physical-implementation level. For the correlator a flexible model is introduced, which enables a comparison of different implementations as well as an analysis of possible trade-offs between silicon area and power dissipation (costs) in a very early design phase. The impact of the correlator-channel parameters on the signal-to-noise-ratio (benefit) are determined by a theoretical analysis and are validated by simulations as well as by measurements. Since the central processing unit has to provide an increased computational performance to process all available GNSSs in parallel, an "Application Specific Instruction Set Processor" (ASIP) optimized for GNSS receiver algorithms is proposed. The exploration of the design space in order to increase the ASIP’s efficiency by using an optimized instruction set as well as tightly coupled application-specific co-processors is described. Finally, "Single Instruction Multiple Data" (SIMD) ASIP architecture, which provides sufficient performance to realize a "Software Defined Radio" (SDR) GNSS receiver, is introduced. It allows for a significantly increased flexibility, as the whole digital receiver processing, including the correlation, can be defined in software