Trade-offs for high yield in 90 nm subthreshold floating-gate circuits by Monte Carlo simulations

The work described in this paper is performed toestimate the influence of statistical process variations andtransistor mismatch that occurs in fabrication and affectfloating-gate digital circuits. These effects will affect and reduce“yield” (percentage of fully functional circuits). Monte Carlosimulations have been performed in a 90 nm to estimate theyield for manufactured floating-gate circuits running withsubthreshold power supply. The power supply, floating-gatecharge voltage (VFGP and VFGN) and transistor sizes have beenvaried during the simulations and the yield has been observed.The simulation results shows that by doubling the minimumsize transistors (length and width) the yield can be much betterthan for minimum size version. A yield of 100% can though notbe expected if the power supply is scaled down below 250 mV. STC - Sensible Things that Communicat