Extraction of interface and border traps in beyond-Si devices by accounting for generation and recombination in the semiconductor

In this work we will apply a novel extraction procedure to characterize interfacial states and border traps in InGaAs and Ge MOSFETs. The extraction technique, which will allow profiling the defect distributions in the (E,z) dielectric bandgap, is based on the simultaneous simulation of C-V and G-V characteristic over a wide frequency range. The impact of minority carrier generation mechanisms taking place in the semiconductor will be deeply investigated, as its impact is essential when the technique is applied to direct low-bandgap semiconductors such as InGaAs and Ge. Results will confirm that the minority carrier generation has to carefully consider to avoid overestimating the extracted defect density