IMECE2004-60041 FCBGA FOOTPRINTS AND SOLDER JOINT RELIABILITY

ABSTRACT As electronic package input/output density increases and cost constraints drive the package size smaller, the one area where a designer can not compromise is solder joint reliability. Maintaining flip chip ball grid array (FCBGA) solder joint reliability (SJR) has been at the top of the designer's critical list with decreasing package size. The FCBGA footprint will need to be modified for a variety of reasons to meet routing optimization, power delivery, electrical performance to name a few. The designer must deal with several competing proposals (electrical performance, cost and use conditions) trying to optimize the FCBGA footprint while being aware that some modifications can negatively affect SJR. This paper investigates solder ball layouts and their effect on SJR through both finite element (FE) models and empirical tests. In addition, consideration of next generation layout is presented to optimize routability while preserving SJR. When feasible, empirical tests were run to validate predictive models. KEYWORDS BGA, Solder Joint Reliability, Layout, FE Modeling INTRODUCTION Flip chip ball grid array (FCBGA) technology has been advancing microprocessors and chipsets into a broader market to address increasing I/O and processing speeds. This places greater demand on the mechanical attributes of the package attachment interface to the board, the solder joint connection or second level interconnect (SLI). The SLI must maintain electrical and mechanical integrity under customer use conditions. To understand the best design tradeoffs finite element models can be used to assess SLI reliability under various customer use conditions to optimize solder pad diameter, solder ball distribution and height