Abstract-Leakage current is susceptible to variation of transistor parameters and environment such as temperature, which results in wide spread in leakage distribution. The spread can be reduced by employing body biasing: reverse body bias for too leaky dies and forward body bias for too slow dies. We investigate body biasing of mixed circuits. It is shown that the conventional body biasing has limitation in reducing leakage variation of mixed circuits. This is because low-and highdevices do not track each other and their body biasing sensitivities are different. We present alternative body biasing scheme that targets compensating die-to-die variation of low . Under this body biasing scheme, within-die profiles of low-and high-, which we ne...
DoctorAggressive technology scaling makes the process variations a significant problem in VLSI desig...
Abstract—This paper presents a novel framework for accurate estimation of key statistical parameters...
Increasing levels of process variability in sub-100nm CMOS design has become a critical concern for ...
[[abstract]]As fabrication technology progresses, several new challenges follow. Among them, the mos...
We present techniques to determine the optimal body bias (forward or reverse) to minimize leakage cu...
[[abstract]]In recent years, fabrication technology of CMOS has scaled to nanometer dimensions. As s...
Nanometer CMOS scaling has resulted in greatly increased circuit variability, with extremely adverse...
ABSTRACT Adaptive body biasing (ABB) is a powerful technique that allows post-silicon tuning of indi...
In modern System-on-Chip (SoC) designs, the fulfillment of power constraints is one of the most impo...
Worst-case design uses extreme process corner conditions which rarely occur. This limits maximum spe...
Worst-case design uses extreme process corner conditions which rarely occur. This costs additional p...
Technology scaling improves the energy, performance, and area of the digital circuits. With further ...
Nanometer CMOS scaling has resulted in greatly increased circuit variability, with extremely adverse...
Abstract — We propose a fine-grained scheme to compensate for within-die variations in dynamic logic...
In this paper, we investigate electrical effects of transistor layout shape (both in the channel and...
DoctorAggressive technology scaling makes the process variations a significant problem in VLSI desig...
Abstract—This paper presents a novel framework for accurate estimation of key statistical parameters...
Increasing levels of process variability in sub-100nm CMOS design has become a critical concern for ...
[[abstract]]As fabrication technology progresses, several new challenges follow. Among them, the mos...
We present techniques to determine the optimal body bias (forward or reverse) to minimize leakage cu...
[[abstract]]In recent years, fabrication technology of CMOS has scaled to nanometer dimensions. As s...
Nanometer CMOS scaling has resulted in greatly increased circuit variability, with extremely adverse...
ABSTRACT Adaptive body biasing (ABB) is a powerful technique that allows post-silicon tuning of indi...
In modern System-on-Chip (SoC) designs, the fulfillment of power constraints is one of the most impo...
Worst-case design uses extreme process corner conditions which rarely occur. This limits maximum spe...
Worst-case design uses extreme process corner conditions which rarely occur. This costs additional p...
Technology scaling improves the energy, performance, and area of the digital circuits. With further ...
Nanometer CMOS scaling has resulted in greatly increased circuit variability, with extremely adverse...
Abstract — We propose a fine-grained scheme to compensate for within-die variations in dynamic logic...
In this paper, we investigate electrical effects of transistor layout shape (both in the channel and...
DoctorAggressive technology scaling makes the process variations a significant problem in VLSI desig...
Abstract—This paper presents a novel framework for accurate estimation of key statistical parameters...
Increasing levels of process variability in sub-100nm CMOS design has become a critical concern for ...