Design of High Performance Phase Locked Loop for UHF Band in 180 nm CMOS Technology

Abstract: The aim of this study was to design low phase noise 2.4 GHz ring oscillator with low power dissipation and small die area. This study presents the design of high performance PLL for UHF band. This PLL has been realized in 180 nm by Virtuoso Analog Design Environment of Cadence tool. After simulating various stages of the ring oscillators, a three-stage ring oscillator has been selected for the implementation of the PLL. A zero dead zone Phase Frequency Detector (PFD) and Charge Pump (CP) with loop filter have been designed and used in the PLL. The PLL has designed with lowest phase noise of-122.2 dBc/Hz @ 10 MHz offset frequency and figure of merit-134 dBc/Hz. The layout of complete PLL has been designed by Virtuoso LayoutXL tool of Cadence. The total area required to implement the PLL without package is (0.093 × 0.09783 mm) 0.0091 mm 2