Dynamic Partial Reconfiguration in Low-Cost FPGAs

Abstract Field Programmable Gate Array (FPGA) market is growing rapidly with various applications in different industries. There is a new concept evolving in FPGA industry called Dynamic Partial Reconfiguration (DPR) with has a greater exposure in different applications. Partial reconfiguration is nothing but reconfiguring the selected areas of an FPGA after its initial configuration at runtime. In this paper we reconfigure some specific region of the FPGA with a new functionality at runtime while the remaining areas remain static during this time. The complexities during the runtime can be simplified by a tool called PlanAhead which was introduced by Xilinx that is able to implement run time reconfigurable systems for all Virtex FPGAs. This results in low computational cost and low power FPGAs, PlanAhead is the first graphical environment for Partial Reconfiguration. In this context Partial Reconfiguration gives the flexibility for reducing the board space (effective utilization of resources), change a design in the field and also reduces the power consumption and delay