Method and System for Automated Unit-Level Testing of FPGA-based Cycle-Accurate Microprocessor Simulator Using Software Simulator as a Golden Model

Abstract For new hard ware/software co-designed CPU architectures there is a need for fast and flexib le performance simu lation to perform extensive design space exp loration in both software and hardware do mains. To confirm reliability of design decisions, the simu lator should also be accurate, which is usually achieved at the cost of reduced simulat ion speed. Although FPGA-accelerated simulators have dramat ically higher speed than software simulators, such models require much higher development effort. An FPGA -based model generally assumes a top-down design flo w, where the system can be tested only after all units have been developed. The paper describes a method and system for bottom-up development and automated unit-level testing of FPGA-based cycle-accurate simulator leveraging functionality of existing software simu lator