Realization of Low Power Sensor Node Processor for Error Detection and Correction in Wireless Sensor Networks

ABSTRACT: Nowadays wireless sensors Networks are used in wide applications. In a large wireless sensor network it consists of sensor nodes .The function of sensor node is sensing, processing and communicating the informations.At the time it consumes dominant power of the total power. In this project design a sensor node with long time operating capability and efficient energy management. Wireless Sensor Networks have potential ability to monitor and interact with our environment. Fault tolerant operation is critical to the success of WSNs.. Noise and other disturbances are the two methods that degrade the system performance. Fault-tolerant mechanism in wireless sensor networks is very important for construction and deployment characteristics of low powered sensing devices. . In this paper we focus our work on implemented with low complexity error detection technique which can be low data redundancy and efficient energy consuming in wireless sensor node. In the sensor node within a single chip has been developed and implemented on a performance Model Sim. Xilinx ISE Simulator has been used to Design the Power Analysis in Using VHDL Coding. An Efficient Sleep scheduling with a Synchronized timer and algorithm to Achieve optimum Power Efficiency