CRYSTALLINITY CONTROL OF ELECTROPLATED INTERCONNECTIONS FOR IMPROVING THEIR STABILITY AND LIFETIME

ABSTRACT In a three-dimensional (3D) packaging systems, the interconnections which penetrate stacked silicon chips have been employed. Such interconnection structure is called TSV (Through Silicon Via) structure, and the via is recently filled by electroplated copper thin film. The electroplated copper thin films often consist of fine columnar grains and porous grain boundaries with high density of defects which don't appear in conventional bulk material. This unique micro texture has been found to cause the wide variation of physical and chemical properties of this material. In the TSV structure, the shrinkage of the copper thin film caused by thermal deformation and recrystallization of the unique texture during high-temperature annealing is strictly constrained by surrounding rigid Si and thus, high tensile residual stress remains in the thin film after thermal annealing. High residual stress should give rise to mechanical fracture of the interconnections and the shift of electronic function of thin film devices formed in Si. Therefore, the residual stress in the interconnections should be minimized by controlling the appearance of the porous boundaries during electroplating for assuring the longterm reliability of the interconnections. As the lattice mismatch between Cu and its barrier film (Ta) is as larger as 18%, which is the main reason for the fine columnar structures and porous grain boundaries, it is necessary to control the underlayer crystallinity to improve the crystallinity of electroplated copper thin films. In this study, the effective method for controlling the crystallinity of the underlayer was investigated by improving the atomic configuration in the electroplated copper thin film. The result showed that by controlling the crystallinity of underlayer、 crystallinity of electroplated copper thin films can be improved, the mechanical properties of thin films was improved and thus, stability and lifetime of electroplated copper interconnections can be improved. INTRODUCTION Nowadays, high reliability and high performance is required for every electronic product in order to assure its safe and comfortable operation. Our household electric appliances such as notebooks, mobile phones, digital cameras, refrigerators, and so on are being miniaturized and lightly weighted. In this way, semiconductor devices are required to have high performance, small size, low cost with high reliability. However, the extreme miniaturization causes new problems such as the increase of resistance of miniaturized interconnections, which increases Joule heating and thus, decreases the lifetime of devices. The miniaturization of a transistor structure also increases the residual stress in the transistor because of the increase in the density of stress concentration fields and the intrinsic stress in each thin film, and thus, causes unexpected variations of its performance and reliability. Based on the above background, a new technology other than miniaturization has become indispensable for improving integrated semiconductor device systems. One of the expected technologies is a three-dimensional (3D) packaging technology which stacks plural Si chips In order to maximize the packaging density of the 3D systems, TSV (Through Silicon Via) structure has been employed, and the vias are filled by metallic thin film