Coupled Simulation to Determine Across Wafer Variations for Electrical and Reliability Parameters of Through-Silicon Vias

Three-dimensional (3D) integration of integrated circuits is a key challenge for the future evolution of semiconductor systems. Through silicon vias (TSV) are an integral component for interconnecting stacked circuits. For the fabrication of TSVs, a sequence of processing steps is required, including etching and deposition. Inevitable variations, for instance across the wafer or due to fluctuations of the equipment parameters, lead to variations of the fabricated structures, which in turn influence their properties, e.g. with respect to a TSV's electrical behavior or reliability. In this work, we demonstrate coupled equipment-and feature-scale process simulation and its application to layer deposition as part of a sequence for the fabrication of TSVs. The resulting structures are studied with respect to their electrical characteristics and reliability by means of finite element (FEM) simulations. Part of the processing sequence studied is the plasma-enhanced chemical vapor deposition (PECVD) of a SiO 2 layer in a capacitively coupled plasma reactor. This work is mainly concerned with the resulting profile of the deposited SiO 2 layer and its variation across the wafer. To model the deposition process we assume that the adsorbed TEOS fragments are saturated on the surface and that the process is therefore governed by the local fluxes of oxygen ions and radicals ). The highfrequency parasitic capacitance does not vary significantly between the differently-located TSVs. This enables a small-signal analysis of the TSV, depicted as an LRC circuit, with an extracted resistance and inductance of approximately 400 mΩ and 4.3 pH, respectively. Acknowledgement The research leading to these results has received funding from the European Union Seventh Framework Programme (FP7/2007(FP7/ -2013 under grant agreement no. 318458 SUPERTHEME