An Estimated Multiplier For Quick Energy-Efficient Digital Indication Dispensation

We propose a high-speed, energy-efficient approximation multiplier. The method is to round the coefficients to the nearest exponent of two. In this way, the abbreviated arithmetic part is omitted from the multiplication process to improve the speed and power consumption with a small error rate. The proposed approach applies to both signed and unsigned complications. We propose that three devices be implemented for the coarse multiplier, which includes one for unsigned and two for signed operations. The efficiency of the proposed multiplier is evaluated by comparing its performance with the performance of some approximate and accurate multipliers using different design criteria. In addition, the effectiveness of the proposed approximate multiplier is studied in two image processing applications, i.e. image sharpening and smoothing