Design of an Efficient AXI-4 Protocol for High Speed SOC Applications on FPGA Platform

The system-on-chip(SoC) design process encounters various challenges of communication between one to another module. Thus, the Bus interconnection plays a significant role in improving the system performance on a single chip. The traditional bus interconnections cease its applicability to meet the requirements of future generation SoC. This paper proposes an efficient design of the AXI-4 protocol to achieve high-speed data transfer in the SoC application. The proposed AXI-4 Interface protocol includes the Master and Slave module, which are designed using state flow and state diagrams. Both the Master and Slave module operations support burst based transactions and perform the five different channel transactions that include “write address,” “write data,” “write a response,” “read address,” “read data” along with “read response.” The simulation results of the AXI-4 interface and its FPGA realization on Artix-7 illustrate lower resource utilization, and the performance benchmarking between proposed AXI-4 with traditional AHB and Wishbone bus modules illustrates an average minimization in area and increase in frequency by 40% and 41% respectively