Configurable memory systems for embedded many-core processors

The memory system of a modern embedded processor con- sumes a large fraction of total system energy. We explore a range of different configuration options and show that a reconfigurable design can make better use of the resources available to it than any fixed implementation, and provide large improvements in both performance and energy con- sumption. Reconfigurability becomes increasingly useful as resources become more constrained, so is particularly rele- vant in the embedded space. For an optimised architectural configuration, we show that a configurable cache system performs an average of 20% (maximum 70%) better than the best fixed implementation when two programs are competing for the same resources, and reduces cache miss rate by an average of 70% (maximum 90%). We then present a case study of AES encryption and decryption, and find that a custom memory configuration can almost double performance, with further benefits being achieved by specialising the task of each core when parallelising the program.This work was funded by the European Research Council grant number 306386.This is the final version. It first appeared on arXiv at http://arxiv.org/abs/1601.00894