Balancing power and performance in DRAM memory controllers

With the developing variance between memory and processor speeds, it has become important to ensure the features of a memory controller are optimized to obtain the maximum possible performance and minimum power consumption from the memory system. This research presents a study of optimization methods in which both power consumption and the overall performance of a DRAM memory controller can be balanced. It contains two presentations that describe these methods and proposed solutions for DRAM memory controllers. The first presentation identifies a process in which power consumption can be reduced without impacting performance. The second presentation offers an approach to optimize both power and performance of the DRAM memory controller. A method using the memory controller features to balance DRAM power and performance is described. The results from these studies show that a significant balance between these two metrics can be obtained by carefully optimizing the logic of the memory controllers to adjust latency, bandwidth, activity factor, and capacitance for power consumption reduction and performance increase