SOI LDMOS with buried multi-finger gates (BFG) is proposed and fabricated. The BFG acts as field plate, modulating the lateral electric field distribution in the drift region (off-state) and enhances the carrier accumulation at the surface of the drift region (on-state). The proposed BFG SOI LDMOS shows a 13.6% increase of breakdown voltage, 24.4% reduction of on-resistance and 14.4% increase of the transconductance compared with the reference SOI LDMOS without BFG
A new 600V Partial Silicon-on-Insulator (PSOI) lateral double-diffused metal-oxide-semiconductor (LD...
[[abstract]]"This article provides a fabricating method to improve significantly both of the breakd...
We investigate planar fully depleted silicon-oninsulator (SOI) MOSFETs with a thin buried oxide (BOX...
A linearly graded doping drift region with step gate structure, used for improvement of reduced surf...
In this paper, we report on the reduction of device resistance by up to 49% in junction isolated lat...
A novel silicon-on-insulator (SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) structu...
[[abstract]]"This article provides a fabricating method to improve significantly both of the breakd...
[[abstract]]This letter demonstrates a successful method for on-state resistance reduction up to 20%...
A concept for the integration of intermitted trench gates into silicon lateral double-diffused metal...
AbstractThe structural modifications in the conventional power laterally diffused metal-oxide-semico...
A novel SOI LDMOS (Lateral Double Diffused MOSfet) structure substituting the PN junction between ch...
[[abstract]]This article provides a method to significantly improve breakdown voltage and specific o...
Abstract — In this letter, we proposed a new layout structure for RF laterally diffused metal-oxide-...
A new device structure named IDLDMOS is proposed to overcome the power LDMOS limit (R-on, (sp) propo...
A novel trench SOI LDMOS with centrosymmetric double vertical field plates structure (CDVFPT SOI LDM...
A new 600V Partial Silicon-on-Insulator (PSOI) lateral double-diffused metal-oxide-semiconductor (LD...
[[abstract]]"This article provides a fabricating method to improve significantly both of the breakd...
We investigate planar fully depleted silicon-oninsulator (SOI) MOSFETs with a thin buried oxide (BOX...
A linearly graded doping drift region with step gate structure, used for improvement of reduced surf...
In this paper, we report on the reduction of device resistance by up to 49% in junction isolated lat...
A novel silicon-on-insulator (SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) structu...
[[abstract]]"This article provides a fabricating method to improve significantly both of the breakd...
[[abstract]]This letter demonstrates a successful method for on-state resistance reduction up to 20%...
A concept for the integration of intermitted trench gates into silicon lateral double-diffused metal...
AbstractThe structural modifications in the conventional power laterally diffused metal-oxide-semico...
A novel SOI LDMOS (Lateral Double Diffused MOSfet) structure substituting the PN junction between ch...
[[abstract]]This article provides a method to significantly improve breakdown voltage and specific o...
Abstract — In this letter, we proposed a new layout structure for RF laterally diffused metal-oxide-...
A new device structure named IDLDMOS is proposed to overcome the power LDMOS limit (R-on, (sp) propo...
A novel trench SOI LDMOS with centrosymmetric double vertical field plates structure (CDVFPT SOI LDM...
A new 600V Partial Silicon-on-Insulator (PSOI) lateral double-diffused metal-oxide-semiconductor (LD...
[[abstract]]"This article provides a fabricating method to improve significantly both of the breakd...
We investigate planar fully depleted silicon-oninsulator (SOI) MOSFETs with a thin buried oxide (BOX...