Processing-in-memory architectures promise increased computing performance at decreased costs in energy, as the physical proximity of the compute pipelines to the data store eliminates overheads for data transport. We assess the overall performance impact using a recently introduced architecture of that type, called the Active Memory Cube, for two representative scientific applications. Precise performance results for performance critical kernels are obtained using cycle-accurate simulations. We provide an overall performance estimate using performance models
International audienceThis work presents a realistic performance model to execute scientific workflo...
Microprocessors and memory systems suffer from a growing gap in performance. We introduce Active Pag...
8th WORKSHOP ON APPLICATIONS FOR MULTI-CORE ARCHITECTURESInternational audienceIn this paper, we ana...
In this talk we will present IBM's Active Memory Cube (AMC) architecture and the outcome of a resear...
Processing-in-memory (PIM) is an approach to address the data transport challenge in future HPC arch...
General purpose processors and accelerators including system-on-a-chip and graphics processing units...
Many modern workloads, such as neural networks, databases, and graph processing, are fundamentally m...
3D integration of solid-state memories and logic, as demonstrated by the Hybrid Memory Cube (HMC), o...
Memory-intensive operations and their memory access latency are often the performance bottleneck in ...
As the performance of DRAM devices falls more and more behind computing capabilities, the limitation...
3D integration of solid-state memories and logic, as demonstrated by the Hybrid Memory Cube (HMC), o...
The complexity of the computational problems is rising faster than the computational platforms' capa...
Memory-based computing (MBC) is promising for improv-ing performance and energy efficiency in both d...
The performance of modern microprocessors is increasingly limited by their inability to hide main me...
With the increase in computational parallelism and low-power Integrated Circuits (ICs) design, neuro...
International audienceThis work presents a realistic performance model to execute scientific workflo...
Microprocessors and memory systems suffer from a growing gap in performance. We introduce Active Pag...
8th WORKSHOP ON APPLICATIONS FOR MULTI-CORE ARCHITECTURESInternational audienceIn this paper, we ana...
In this talk we will present IBM's Active Memory Cube (AMC) architecture and the outcome of a resear...
Processing-in-memory (PIM) is an approach to address the data transport challenge in future HPC arch...
General purpose processors and accelerators including system-on-a-chip and graphics processing units...
Many modern workloads, such as neural networks, databases, and graph processing, are fundamentally m...
3D integration of solid-state memories and logic, as demonstrated by the Hybrid Memory Cube (HMC), o...
Memory-intensive operations and their memory access latency are often the performance bottleneck in ...
As the performance of DRAM devices falls more and more behind computing capabilities, the limitation...
3D integration of solid-state memories and logic, as demonstrated by the Hybrid Memory Cube (HMC), o...
The complexity of the computational problems is rising faster than the computational platforms' capa...
Memory-based computing (MBC) is promising for improv-ing performance and energy efficiency in both d...
The performance of modern microprocessors is increasingly limited by their inability to hide main me...
With the increase in computational parallelism and low-power Integrated Circuits (ICs) design, neuro...
International audienceThis work presents a realistic performance model to execute scientific workflo...
Microprocessors and memory systems suffer from a growing gap in performance. We introduce Active Pag...
8th WORKSHOP ON APPLICATIONS FOR MULTI-CORE ARCHITECTURESInternational audienceIn this paper, we ana...