The DEEP project implements a novel architecture for high-performance computing consisting of two components - a standard HPC-Cluster and a "Booster" cluster of many-core processors. The Cluster part is built from Intel Xeon multicore processors connected via InfiniBand while the Booster part utilizes Intel Xeon Phi cards and the highly scalable EXTOLL network.This paper describes a forwarding protocol that bridges both interconnects in a highly efficient way. It uses EXTOLL's unique shared memory functional unit to enable transfers of network payload between InfiniBand an EXTOLL. The current implementation delivers nearly 99% of the expected peak performance on an evaluation system
IP forwarding is one of the main bottlenecks in Internet backbone routers, as it requires performing...
Abstract—Current leadership-class machines suffer from a significant imbalance between their increas...
We can design high-frequency soft-processors on FPGAs that exploit deep pipelining of DSP primitives...
On the way towards Exascale the needed hardware for supercomputing is struggling to keep delivering ...
Homogeneous cluster architectures, which used to dominate high-performance computing (HPC), are chal...
On the way to explore the path to Exascale, the DEEP/-ER projects take a radically different approac...
Interconnecting multiple clusters with a high speed net-work to form a single heterogeneous architec...
Cluster computers are dominating high-performance computing (HPC) today. The success of this archite...
Striving at pushing the applications scalability to the limits, the DEEP project proposed an alterna...
Accelerators arrived to HPC when the power bill for achieving Flop performance with traditional, hom...
Improving the performance of future computing systems will be based upon the ability of increasing t...
Cluster computers are dominating high performance computing (HPC) today. The success of this archite...
The European Dynamical Exascale Entry Platform (DEEP) is an example of a new type of heterogeneous s...
HyperTransport 3.10 is the best open standard communication technology for chip-to-chip interconnect...
During the last decades the ever growing need for computational power fostered the development of pa...
IP forwarding is one of the main bottlenecks in Internet backbone routers, as it requires performing...
Abstract—Current leadership-class machines suffer from a significant imbalance between their increas...
We can design high-frequency soft-processors on FPGAs that exploit deep pipelining of DSP primitives...
On the way towards Exascale the needed hardware for supercomputing is struggling to keep delivering ...
Homogeneous cluster architectures, which used to dominate high-performance computing (HPC), are chal...
On the way to explore the path to Exascale, the DEEP/-ER projects take a radically different approac...
Interconnecting multiple clusters with a high speed net-work to form a single heterogeneous architec...
Cluster computers are dominating high-performance computing (HPC) today. The success of this archite...
Striving at pushing the applications scalability to the limits, the DEEP project proposed an alterna...
Accelerators arrived to HPC when the power bill for achieving Flop performance with traditional, hom...
Improving the performance of future computing systems will be based upon the ability of increasing t...
Cluster computers are dominating high performance computing (HPC) today. The success of this archite...
The European Dynamical Exascale Entry Platform (DEEP) is an example of a new type of heterogeneous s...
HyperTransport 3.10 is the best open standard communication technology for chip-to-chip interconnect...
During the last decades the ever growing need for computational power fostered the development of pa...
IP forwarding is one of the main bottlenecks in Internet backbone routers, as it requires performing...
Abstract—Current leadership-class machines suffer from a significant imbalance between their increas...
We can design high-frequency soft-processors on FPGAs that exploit deep pipelining of DSP primitives...