The impact of technology scaling on integrated analogue CMOS RF front-ends for wireless applications

This work investigates the impact of recent CMOS process technology shrinks on analogue integrated circuit design. Two LNAs in a wireless communication application serve as an application example for the investigation. Two LNAs have been implemented in a contemporary 65nm standard CMOS process technology for usage in a low-cost low-power mobile 2.5G GSM receiver front-end. The first LNA serves the GSM low bands whereas the second LNA serves the GSM high bands. The underlying LNA architecture, consisting of two cascaded differential stages with capacitive feedback, achieves appropriate gain, noise and linearity performance at moderate current consumption while omitting die area consuming integrated inductors. The LNAs are embedded into the zero-IF receiver front-end of a complete GSM SoC transceiver solution that will enter mass production by the beginning of 2009. Due to the manifold interdependencies and interactions with other receiver front-end components like the quadrature down-conversion mixer, the LNAs have been designed and evaluated in the context of a complete analogue receiver front-end in close cooperation with a business partner from the industrial wireless communication background. The performance specifications for the receiver front-end and the individual circuit blocks have been derived directly from the official 3GPP GSM system specifications. With the specification requirements in mind it has been elaborated on the choice of a direct-conversion receiver as the most reasonable wireless receiver topology for low-cost mass-production in standard CMOS technologies. Design challenges i.e. the impact of flicker noise on the receiver sensitivity are countered by an innovative mixer architecture with a passive current-commutating stage and a careful design of the receiver baseband circuit blocks. The developed GSM transceiver is a transfer and adaptation of a 130nm GSM chip to the special environment introduced by a 65nm low-power CMOS process technology. Consequently the impact of CMOS technology scaling on analogue and RF circuit design in terms of amplifying potential, noise and linearity performance has been analysed in a profound model based comparison of transistor unit cells and passive components in a 130nm and a 65nm CMOS process technology. It is illustrated that the amplifying potential of transistors gM/gDS with minimum gate lengths l is severely deteriorated when going from l=120nm to l=60nm devices. Moreover, an inferior noise performance is observed for minimum channel length transistor devices. It is also shown that for realistic bias conditions the individual transistor device with l=60nm exhibits less odd order distortion than with l=120nm. The performance of the designed and implemented analogue circuit blocks of the receiver frontend have been evaluated by pre-layout and post-layout circuit simulation results with a special focus on the LNAs. The LNAs achieve satisfactory S1118.3dB, CP1i>22.8dBm and IIP3>-14.1dBm in all four GSM frequency bands. The noise figures are an excellent NF58.3 dB and NF54.0dB and NF-16.3dBm while IIP2>42.2dBm. The good accordance between simulation results and measurement results gives rise to superior product-ready performance expectations for future testchips. The overall transfer of the receiver front-end under investigation from a 130nm CMOS technology to a 65nm technology is considered successful. The work is concluded by a summary of prospects of future CMOS process technology nodes with respect to analogue and RF circuit design. After the constraints and limits of conventional deep sub-micron CMOS devices have been pointed out, light is shed on promising approaches to overcome these roadblocks on the ITRS. The ongoing shrink of CMOS process technologies is driven by the semiconductor manufacturers’ desire to integrate given electrical functionality on less die area and consequently reduce the production costs in mass production. Thus the economical benefits of future CMOS process technology shrinks are briefly investigated. It is stressed that significant economical benefits result only for the miniaturisation of systems with a large amount of digital functionality of extended feature sets