Influence of low temperature thermal annealing on the performance of microcrystalline silicon thin-film transistors

Top-gate staggered microcrystalline silicon thin-film transistors (mu c-Si:H TFTs) were prepared by plasma enhanced chemical vapor deposition at temperatures below 200 degrees C. The mu c-Si:H TFTs exhibit high effective electron mobilities (device mobilities) of up to 35 cm(2)/V s for long channel devices. Due to the high carrier mobility mu c-Si:H TFTs are promising devices for large area electronics such as organic light-emitting diode displays or radio frequency identification devices. The fabrication process of the mu c-Si:H TFTs is similar to the fabrication process of amorphous silicon thin-film transistors, which facilitates an easy transfer of the technology to industry. In this paper, the influence of postfabrication low temperature thermal annealing (150 degrees C) on the device properties of top-gate staggered mu c-Si:H TFTs is investigated. Low temperature thermal annealing reduces the device threshold voltage and subthreshold slope. Furthermore, the annealing step results in an increase of the effective mobility for long channel transistors, whereas the effective mobility for short channel transistors is reduced. The influence of the postfabrication low temperature thermal annealing on the device performances will be discussed in detail. (c) 2007 American Institute of Physics