Voltage partitioning on functional units/blocks targeting peak power minimization has been demonstrated to be effective for energy reduction considering voltage island shutdown impact. However, the existing technique can only solve this NP-hard problem efficiently on small designs. In this paper, a much faster linear time approximation scheme is proposed, which can approximate the optimal voltage partitioning solution within a factor 1+, for any 0 \u3c \u3c 1, and runs in O(n + 1/O(1)) time, where n is the number of functional units. There are multiple ingredients in such a surprisingly low time complexity algorithm. It first categorizes all the functional units into big functional units and small functional units using an related thres...
With today\u27s increasingly large and complex digital integrated circuit (IC) and system-on-chip de...
This paper deals with power minimization problem for data-dominated applications based on a novel co...
Abstract—In this paper, we design and implement an effi-cient algorithm for extreme event screening ...
With advancing technology, large dynamic power consumption has significantly limited circuit miniatu...
Increasing transistor density in nanometer integrated circuits has resulted in large on-chip power d...
Reducing power consumption through high-level synthesis has attracted a growing interest from resear...
Abstract:- We present a multiple-voltage high-level synthesis methodology that minimizes power dissi...
In this paper, a tabu-search-based behavior level synthesis scheme is proposed to minimize chip powe...
This paper presents a time-constrained algorithm and a resource-constrained algorithm to minimize th...
Dynamic voltage scaling and adaptive body biasing have been shown to reduce dynamic and leakage powe...
Dynamic voltage scaling and adaptive body biasing have been shown to reduce dynamic and leakage powe...
In this paper we propose a system level power optimization problem : A problem to assign optimal VD...
Energy-efficiency has been an important system issue in hardware and software designs for both real-...
As VLSI technology reaches 45nm technology node, leakage power optimization has become a major desig...
Power consumption is an increasing concern in real-time systems that operate on battery power or r...
With today\u27s increasingly large and complex digital integrated circuit (IC) and system-on-chip de...
This paper deals with power minimization problem for data-dominated applications based on a novel co...
Abstract—In this paper, we design and implement an effi-cient algorithm for extreme event screening ...
With advancing technology, large dynamic power consumption has significantly limited circuit miniatu...
Increasing transistor density in nanometer integrated circuits has resulted in large on-chip power d...
Reducing power consumption through high-level synthesis has attracted a growing interest from resear...
Abstract:- We present a multiple-voltage high-level synthesis methodology that minimizes power dissi...
In this paper, a tabu-search-based behavior level synthesis scheme is proposed to minimize chip powe...
This paper presents a time-constrained algorithm and a resource-constrained algorithm to minimize th...
Dynamic voltage scaling and adaptive body biasing have been shown to reduce dynamic and leakage powe...
Dynamic voltage scaling and adaptive body biasing have been shown to reduce dynamic and leakage powe...
In this paper we propose a system level power optimization problem : A problem to assign optimal VD...
Energy-efficiency has been an important system issue in hardware and software designs for both real-...
As VLSI technology reaches 45nm technology node, leakage power optimization has become a major desig...
Power consumption is an increasing concern in real-time systems that operate on battery power or r...
With today\u27s increasingly large and complex digital integrated circuit (IC) and system-on-chip de...
This paper deals with power minimization problem for data-dominated applications based on a novel co...
Abstract—In this paper, we design and implement an effi-cient algorithm for extreme event screening ...