As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignment manifests enormous potential in drastically reducing wire delay. This is due the fact that wires on thick metals are much less resistive than those on thin metals. Nevertheless, it is not desired to assign all wires to thick metals and the right strategy is to only use minimal thick-metal routing resources for meeting the timing constraints. This timing driven minimum cost layer assignment problem is NP-Complete, and a fast algorithm with provable approximation bound is highly desired. In this paper, a new fully polynomial time approximation scheme is proposed. I...
As VLSI technology scales to deep sub-micron and beyond, it becomes increasingly challenging to ach...
We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according ...
The design scale of Integrated Circuits (ICs) is increasing exponentially according to Moore's law, ...
As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit...
As VLSI technology enters the nanoscale regime, the interconnect delay becomes the bottleneck of cir...
[[abstract]]Given the geometry of wires for interconnections, the authors want to assign two conduct...
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the ...
In this paper, we study the optimal wiresizing problem under the distributed Elmore delay model. We ...
As technology scaling advances beyond 65 nanometer node, more devices can fit onto a chip, which imp...
Abstract—For the last several technology generations, VLSI designs in new technology nodes have had ...
This paper addresses a delay-driven layer assignment problem with consideration of via delay and cou...
For the last several technology generations, VLSI designs in new technology nodes have had to confro...
The sustained progress of VLSI technology has altered the land-scape of routing which is a major phy...
As the continuous trend of Very Large Scale Integration (VLSI) circuits technol-ogy scaling and freq...
In this paper, we study the optimal wiresizing problem for nets with multiple sources under the RC t...
As VLSI technology scales to deep sub-micron and beyond, it becomes increasingly challenging to ach...
We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according ...
The design scale of Integrated Circuits (ICs) is increasing exponentially according to Moore's law, ...
As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit...
As VLSI technology enters the nanoscale regime, the interconnect delay becomes the bottleneck of cir...
[[abstract]]Given the geometry of wires for interconnections, the authors want to assign two conduct...
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the ...
In this paper, we study the optimal wiresizing problem under the distributed Elmore delay model. We ...
As technology scaling advances beyond 65 nanometer node, more devices can fit onto a chip, which imp...
Abstract—For the last several technology generations, VLSI designs in new technology nodes have had ...
This paper addresses a delay-driven layer assignment problem with consideration of via delay and cou...
For the last several technology generations, VLSI designs in new technology nodes have had to confro...
The sustained progress of VLSI technology has altered the land-scape of routing which is a major phy...
As the continuous trend of Very Large Scale Integration (VLSI) circuits technol-ogy scaling and freq...
In this paper, we study the optimal wiresizing problem for nets with multiple sources under the RC t...
As VLSI technology scales to deep sub-micron and beyond, it becomes increasingly challenging to ach...
We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according ...
The design scale of Integrated Circuits (ICs) is increasing exponentially according to Moore's law, ...