Performance analysis of future system-on-FPGA topology candidates

New System-on-Chip (SoC) design techniques are necessary to address the communication requirements for future SoC. The currently used Bus-Centered approach becomes an inappropriate choice because of its limitation as a shared medium that restricts the scalability of the communication architecture. Also, long bus wires result in performance degradation due to the increased capacitive load. The long wires also consume more power to drive all of Intellectual Property Cores, IP Cores, on the bus. New communication architecture, the NoFPGA (Network-on-FPGA), for future SoFPGA (System-on-FPGA) has been presented. The paper details the architecture of a NoFPGA router. The interconnecting issues in SoC design methodology built in a single FPGA device are addressed. Mainly, the problem of achieving efficient NoFPGA performance through investigating the best topology is addressed. Results of the work show that the 2D Torus NoFPGA outperforms the 2D Mesh NoFPGA. On the other hand, Power estimate analysis showed that the Mesh NoFPGA represents a 30% power drop compared to the equivalent Torus NoFPGA which makes the Mesh NoFPGA is a better candidate for power critical application. © 2009 IEEE